The manufacture of ultra-large scale integrated circuits typically involves a chemical-mechanical planarization (CMP) step in which a patterned copper surface is subjected to a polishing process using a combination of abrasives and chemical agents. This CMP step is typically followed by a post-CMP clean step (pCMP) to remove residues left by the CMP step from the semiconductor work-piece surface without significantly etching the metal, leaving deposits on the surface, or imparting significant organic carbonaceous contamination to the semiconductor work-piece. Ideally, the cleaned work-piece proceeds immediately after the pCMP process into a vacuum environment for the next step of the manufacturing process. Because of queue time-related delays between wet and dry tools, work-pieces coming out of pCMP clean do not always promptly enter a vacuum (air-free) environment for the next process step, and surface copper oxide formation occurs. This oxide compromises device performance and must be removed from the copper surface prior to the deposition of the next layer in the preparation of copper interconnects on semiconductor chips. In the dual damascene process, the next layer is typically a silicon nitride cap layer deposited by plasma enhanced physical vapor deposition (PECVD).
The copper oxide layer is currently removed from the copper surface following pCMP cleaning steps by a plasma clean process. Although this plasma clean is effective, the exposure of the dielectric material surrounding the copper lines to the plasma during the cleaning cycle damages the dielectric material. With the introduction of more fragile low k dielectric materials in current and future generations of chips, this damage could be significant and could change the dielectric properties of the material, leading to failures.
In another step in chip fabrication, the semiconductor wafer is etched to create a pattern of vias and interconnect lines, followed by cleaning with a post-etch residue (PER) remover to clean the wafer of any debris resulting from the etching step. Copper lines exposed during the etching step are susceptible to copper oxide formation on contact with the ambient atmosphere. As in the case of pCMP cleaning, any copper oxide formed must be removed prior to deposition of the next layer, typically a barrier layer followed by copper layers. Typically, the copper oxide layer is removed via a plasma clean step that can damage the dielectric layer.
Copper surfaces exposed following pCMP cleaning and post-etch PER removal are susceptible to oxidation owing to the exposure of the copper surface to the ambient atmosphere.
A process is needed to prevent the formation of copper oxide on semiconductor work-pieces that is compatible with chip manufacturing processes and that does not damage sensitive dielectric layers.